点时钟DCLK由处理器DSP的系统时钟40MHz经数字锁相环二分频得到。点时钟驱动行时序生成器,产生图2所示的行同步信号HS和行消隐信号HB。为避免毛刺,控制器设计采用同步设计方法,如图3所示,行同步信号HS通过一个微分电路,产生一个点时钟周期宽的场时序生成器使能信号。在使能信号有效时,场时序生成器开始计数,并产生场同步信号VS和场消隐信号VB。行消隐信号HB和场消隐信号VB相与后即为数据使能信号DATA_EN。该数据使能信号作为产生帧存地址计数器的计数使能,以保证DATA_EN信号为高时,将象素送给AMLCD显示。在DCLK的上升沿,帧存地址计数器加一,帧存SRAM经过一段延时后,象素数据出现在总线上。在DCLK的下降沿AMLCD将数据读入。该LCD控制器的设计方法很容易用于VGA视频接口。在VGA接口电路的设计中,不需点时钟电路,只须将行同步信号与场同步信号输出,将数据使能信号作为复合消隐信号输入即可。产生行场扫描时序的VHDL描述如下:
entity seq_gen is
port(clk_seq : in std_logic;
rst_seq : in std_logic;
lcd_hs_out : out std_logic;
lcd_dataen : out std_logic;
lcd_vs_out : out std_logic;
pix_clk : out std_logic );
end seq_gen;
architecture rtl_seq_gen of seq_gen is
signal lcd_hb : std_logic;
signal lcd_hs : std_logic;
signal lcd_vb : std_logic;
signal lcd_vs : std_logic;
signal clken_vcount : std_logic;
begin
hcount: block
signal hcountreg :std_logic_vector(9 downto 0);
signal hz_temp : std_logic;
signal lcd_hz : std_logic;
begin
process (clk_seq,lcd_hz)
begin
if (lcd_hz = ‘1‘) then
hcountreg <= (others =>‘0‘);
elsif clk_seq‘event and clk_seq = ‘1‘ then
hcountreg <= hcountreg +1;
end if;
end process;
lcd_hb <= ‘0‘ when hcountreg >=600 and hcountreg < 650
else ‘1‘;
lcd_hs <=‘0‘ when hcountreg >=610 and hcountreg < 630
else ‘1‘;
hz_temp <= ‘1‘ when hcountreg = 650 else ‘0‘;
lcd_hz <=hz_temp or rst_seq;
end block hcount;
diff : block
signal inputrega : std_logic;
signal inputregb : std_logic;
begin
process(clk_seq)
begin
if clk_seq‘event and clk_seq=‘1‘ then
inputregb <= inputrega;
inputrega <= not lcd_hs;
end if;
end process;
clken_vcount <= not inputregb and inputrega;
end block diff;
vcount : block
signal vcountreg : std_logic_vector(9 downto 0);
signal vz_temp : std_logic;
signal lcd_vz : std_logic;
begin
process (clk_seq,lcd_vz)
begin
if(lcd_vz=‘1‘)then
vcountreg <= (others => ‘0‘);
elsif clk_seq‘event and clk_seq = ‘1‘ then
if clken_vcount = ‘1‘ then
vcountreg <= vcountreg +1;
end if;
end if;
end process;
lcd_vb <= ‘0‘ when vcountreg >=600 and vcountreg < 615
else ‘1‘;
lcd_vs <=‘0‘ when vcountreg >=607 and vcounreg < 610
else ‘1‘;
vz_temp <= ‘1‘ when vcountreg = 615 else ‘0‘;
lcd_vz <= vz_temp or rst_seq;
end block vcount;
pix_clk <=clk_seq;
lcd_dataen <=lcd_hb and lcd_vb;
lcd_hs_out <=lcd_hs;
lcd_vs_out <=lcd_vs;
end rtl_seq_gen;
这种用VHDL产生扫描时序的方法简单、易读,并且易于修改。在代码中只须修改一些时序参数就能产生任意时序的波形,具有很好的可重用性。用FPGA Express 3.5半VHDL代码综合后,通过Foundation 3.1i进行布局和布线,用Foundation提供的门级仿真工具产生的行扫描时序仿真图如图4所示。
采用FPGA技术设计的AMLCD控制器,大大减少了电路板的尺寸,同时增加了系统可靠性和设计灵活性。这种用VHDL语言实现现行场扫描时序生成器的方法,具有简便。易读和可重用性强的特点。该AMLCD控制器已用Xilinx公司的SpartanII系列器件XC2S50实现,并在飞机座舱图形显示系统中实现应用。
作者: 李小路 时间: 2021-6-23 15:18
谢谢分享!