always@(posedge CLK or negedge RST_n) begin
if (RST_n) begin
x_cnt <= 11'd0;
hd <= 1'd0;
end
else if (x_cnt ==479) begin
x_cnt <= 11'd0;
hd <= 1'd0;
end
else begin
x_cnt <= x_cnt + 11'd1;
hd <= 1'd1;
end
end
always@(posedge CLK or negedge RST_n) begin
if (iRST_n)
y_cnt <= 10'd0;
else if (x_cnt == 479) begin
if (y_cnt == 271)
y_cnt <= 10'd0;
else
y_cnt <= y_cnt + 10'd1;
end
end 1.3 ADS7843 芯片控制器的设计