由于篇幅有限,以下只给出Module 2的VHDL语句,具体如下:
LIBRARY ieee;
USE ieee.STd_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY Module2 IS
PORT ――定义端口
( clk :IN std_logic;
q :OUT std_logic_vector(3 DOWNTO 0)
);
END Module2;
ARCHITECTURE Module2 of Module2 IS
BEGIN
PROCESS(clk)
VARIBLE sum:integer:=0; ――定义变量sum,初值为0
BEGIN
IF(clk’event AND clk=’1’)THEN
sum:=sum+1; ――clk为上升沿时,sum加1
IF(sum>=5)THEN
sum:=1;
END IF;
END IF;
CASE sum IS ――根据sum输出相应的值
WHEN 1 => q<=“1110”;
WHEN 2 => q<=“1101”;
WHEN 3 => q<=“1011”;
WHEN 4 => q<=“0111”;
WHEN THERS => q<=“1111”;
END CASE;
END PROCESS;
END Module2;