2． 在max7000系列中, 只允许有两个输出使能信号, 可在设计中却存在三个, 每次编译时出现“device need too many [3/2] output enable signal”. 如果不更换器件（使用的是max7064lc68）. 如何解决这个问题？
答：Each of these unique output enables may control a large number of tri-stated signals. For example, you may have 16 bidirectional I/O pins. Each of these pins require an output enable signal. If you group the signals into a 16-bit bus, you can use one output enable to control all of the signals instead of an individual output enable for each signal. （参考译文：这两个独特的输出使能中每个都可能控制大量三相信号. 例如, 可能有16个双向I/O引脚. 每个引脚需要一个输出使能信号. 如果将这些信号一起分组到一个16位总线, 就可以使用一个输出使能控制所有信号, 而不用每个信号一个输出使能. ）
3． 关于vhdl的问题：process(a, b, c) begin… end process; 如果a、b、c同时改变, 该进程是否同时执行三次？
4． 在设计最初, 由于没有将时钟信号定义在全局时钟引脚上, 导致MAXPLUS II 在时间分析时提示错误：（时钟偏斜加上信号延迟时间超过输入信号建立时间）. 全局时钟引脚的时钟信号到各个触发器的延时最小, 有没有可能通过编译软件设置, 将普通I/O脚上的时钟信号也经过芯片内部的快速通道以最小的延迟送到每个触发器时钟引脚？
答：you can register that signal and assign it as the global signal, by the step flow: assign->logic option->Individual logic options->Global signal. But you'd better input the clock signal through the dedicated input pin. （参考译文：可以寄存这个信号, 并将它指定为全局信号, 步骤如下：指定—>逻辑选项—>个别逻辑选项—>全局信号. 但是, 最好通过专用输入引脚输入时钟信号. ）
11． 在Xilinx Foundation 3. 1i下用JTAG PROGRAMER下载程序到芯片中, 可是总是出现如下错误：If the security flag is turned on in the bitstream, programming status can not be confirmed;others, programming terminated due to error. 测量电路信号, 没有相应的波形, 显然下载没有成功. 所用的芯片是：Xilinx Spartan2 XC2S50TQ144. 怎么解决？
答：This is a security feature. By disabling readback, the configuration data cannot be read back from the FPGA. This prevents others from pirating your intellectual properties. You can enable or disable this feature during bitstream generation.
The proper way to determine if the configuration is finished without error is to check the status of the DONE pin on the FPGA. DONE pin should goes high if the bitstream is received correctly. Also, since you are using JTAG configuration, please make sure you have selected JTAG clock (not CClk) as your Startup clock during bitstream generation. （参考译文：这是保密功能. 通过禁用回读, 配置数据不能从FPGA回读. 这可以防止其他人盗用你的成果. 在生成位元流过程中, 可以启用或禁用这个功能.
答：Most synthesis tools (e. g. Synplify Pro, Xilinx XST) are able to infer LUT based shift register (SRL16E) from your source code. Even for depth greater than 16, the tool is smart enough to infer multiple SRL16E to realize the shift register. Another way to utilize this feature is to instantiate an SRL16E in the source code. You can refer to the Library Guide in the Xilinx ISE software package for more details. （参考译文：大多数综合工具, 例如Synplify Pro和Xilinx XST, 都能根据源代码中的移位寄存器SRL16E来推断 LUT. 即使是深度大于16的情况, 此类工具也能够推断出多SRL16E, 从而实现移位寄存器. 利用此功能的另一种途径是在原代码中例示一个SRL16E. 详细说明可以参考Xilinx ISE软件包中的库指南. ）
答：The LUTs in Xilinx Virtex architecture are not simply combinational logic. When it is configured as 16x1 RAM, the write operation is synchronous. When it is configured as shift register, there is no need to consume any flip-flop resource. In fact the internal circuitry of a Virtex LUT is more complicated than what it looks like. （参考译文：Xilinx Virtex结构中的LUT不是简单的组合逻辑。当它被配置为16x1 RAM时，写操作是同步的。当它被配置为移位寄存器时，则无需消耗任何flip-flop资源。事实上Virtex LUT的内部电路比看起来更复杂。）
答：Here are a few guidelines for reliable FPGA design（关于可靠性FPGA设计的几点建议）
① Use fully synchronous design. Asynchronous design is very sensitive to path delay and is therefore not robust. An example of asychronous circuit is the SR latch which uses combinational feedback. （使用完全同步设计. 异步设计对路径延迟非常敏感, 因此不很可靠. 异步电路的一个例子是使用组合反馈的SR闭锁. ）
② Never gate your clock signal with combinational logic. Glitches may occur on any gated clock signals, which results in false triggering of flip-flops. （绝不使用组合逻辑控制时钟信号. 因为在任何门控制时钟信号上可能产生短时脉冲干扰, 最终导致错误触发flip-flop. ）
③ Never rely on gate delay. （绝不要依靠门延迟. ）
④ Enough bypass capacitors should be placed close to the power and ground pins of FPGA. Use capacitors with good high frequency response. （FPGA的电源和接地引脚附近应该放置足够多的旁路电容器. 使用优质高频响应电容器. ）
⑤ Always use the global clock buffers on the FPGA to drive internal clock signals. These clock buffers and the associated clock distribution network have been carefully designed to minimize skew. （在FPGA上始终使用全局时钟缓冲来驱动内部时钟信号. 并且已经仔细设计了这些时钟缓冲和关联时钟配电网, 以将畸变减至最小. ）
27． You said "An example of asychronous circuit is the SR latch which uses combinational feedback". How do I learn SR latch ? What is the difference between SR latch and SRFF? （“异步电路的一个例子是使用组合反馈的SR闭锁”. 请问如何理解SR闭锁？SR闭锁与SRFF有什么区别？）
答：A latch changes states whenever the gate signal is active. A FF changes states only at clock edges. （参考译文：只要门信号是活动的, 闭锁就会更改状态. 而FF只有在时钟边沿才更改状态. ）
28． Xilinx公司的芯片在热设计方面可以提供哪些工具和资料？
答：For thermal consideration, you need to know the power consumption of your FPGA and the thermal resistivity of the device package you are using. The power consumption can be estimated by the XPower tool included in Xilinx ISE software. The thermal resistivity of the device package can be found in Xilinx databook. The junction temperature can then be calculated by the following formula（至于散热问题, 需要了解所用FPGA的功耗和正在使用的器件封装的热阻系数. Xilinx ISE软件中所包含的Xpower工具可以估计功耗. 在Xilinx数据手册中可以找到器件封装的热阻系数. 然后利用下面的公式计算接合温度. ）
You can then detemine if the junction temperature falls within the acceptable region. The maximum acceptable junction temperature is different for C and I grade devices. If it is higher than the max. acceptable temperature, you may consider adding a heatsink or cooling fan. （之后确定接合温度是否在允许范围内. C和I级器件允许的最高接合温度不同. 如果温度高于允许的最高值, 可能需要增加散热片或风扇. ）
答：Gating the clock signal with combinational logic is not recommended in modern high speed digital design since it may creates glitches on the gated clock signal, which results in false triggering of flip-flops. This results in a less reliable design. A common technique to remove gated clock is to make use of the clock enable pin of the flip-flop. For example, if you have a signal clko = clki & a & b driving the clock pin of a flip-flop, you can eliminate the gated clock by feeding clki directly to the FF clock pin, and have another signal en = a & b connected to the clock enable pin of the FF. ( 参考译文：在现代高速数字设计当中, 不建议使用组合逻辑门控时钟信号, 因为这将会在选通的时钟信号上产生短时脉冲波形干扰, 导致错误触发flip-flop. 这是缺乏可靠性的设计. 移除门控时钟通常所采用的技巧是使用flip-flop的时钟使能引脚. 例如, 如果有一个信号clko = clki & a & b 正在驱动flip-flop的时钟引脚, 则可以通过直接将clki传递给FF时钟引脚, 并将另一个信号en = a & b与FF的时钟使能引脚连接, 来消除门控时钟. )
By removing the gated clock, you no longer have the problem of clock delay. Also the design is more robust. (移除门控时钟后, 就不再有时钟延迟的问题了. 而且这种设计也比较可靠. )
30． FPGA生产产商提供了IP, 如何用第三方软件, 如Advantage 或 ACTIVE vhdl, 调用并进行仿真？
答：The IPs provided by Xilinx, e. g. PCI, come with simulation models which can be processed by 3rd part simulation tools like Modelsim. So there is no problem for functional simulation. Timing simulation can be done by exporting the post-layout vhdl/verilog model from Xilinx ISE software. In some cases, sample testbenches are also included. （参考译文：Xilinx提供的IP, 例如PCI, 是与仿真模型一同提供的, 这种模型可由第三方仿真工具, 如Modelsim来处理. 因此对功能仿真来说, 没有问题. 通过从Xilinx ISE软件中导出post-layout vhdl/verilog可以执行定时仿真. 在某些情况下, 也包括样本测试平台. ）
31． “As a good design practice, never use gate delay to implement your delay logic under all circumstances”. Please tell me what does "gate delay"(闸) mean?（“一个好的设计, 在所有情况下都决不会使用门延迟来实现延迟逻辑. ”此处“门延迟”是什么意思？）
答： “By "gate delay" I mean using a series of logic gates to introduce certain amount of delay in the design. This is highly undesirable since gate delay changes with factors like temperature and process technology. The design may fail as temperature changes or using a different version silicon. Also designs relying on gate delay are not portable, meaning that you need to re-design the whole circuit whenever you want to change to another product series or part number, simply because the gate delay changes as well. （参考译文：“门延迟”指得是使用一系列逻辑门将一定数量的延迟导入到设计中. 既然门延迟更改像温度和处理技术这样的因素, 所以, 这是很不合适的. 由于温度的改变或使用不同版本的芯片, 设计可能会失败. 依赖门延迟的设计也不是可移植的, 也就是说, 要更改另一产品系列或部件号时, 需要重新设计整个电路, 只因为更改了门延迟. ）
Always use fully synchronous design. You never need to reply on gate delay if your design is fully synchronous. （始终使用完全同步设计. 如果设计是全同步的, 则无需回应门延迟. ）
32． This time I download another program to another chip SpartanII XC2S50PQ208 in another circuit, while it fails, and show the following message: ". . . Checking boundary-scan chain integrity. . . ERROR:JTag - Boundary-scan chain test failed at bit position '3' on instance '***'(a substitute for the real name of file). A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. ERROR:JTag - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. " With so many messages, I don't know what to do! I try many times but only fail, and doubt whether there is something wrong with the circuit?But the powers checked in circuit are right. Would you please give me some advice to crack the problem?（有一次, 将程序下载至SpartanII XC2S50PQ208芯片电路, 结果发生了故障, 并显示以下消息：“. . . Checking boundary-scan chain integrity. . . ERROR:JTag - Boundary-scan chain test failed at bit position '3' on instance '***'(实际的文件名)”. 问题可能在硬件配置. 检查了连线、扫描链路和电源接头都没有问题. 特定的扫描链路配置与实际的硬件相匹配, 电源充足且电压正常. “ERROR:JTag - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. ”这么多出错消息, 什么原因, 怎么办？）
答：Usually it is the result of a broken JTAG chain or noisy chain. Most commonly, the cable is not connected properly, a trace is not correct on the board, other devices in the chain are causing a problem, or a noisy parallel port exists. Try using a different PC. You can also add a 4. 7K pullup on the PROG pin of the FPGA and see if it helps. （通常, 这是由于中断的JTAG链或噪声链. 最常见的原因是, 连线不正确, 板子上的迹线不正确, 链路中的其它器件导致问题, 或者存在噪声并口. 试一下使用不同的PC. 也可以在FPGA的PROG引脚上增加一个4. 7K的上拉电阻, 看看是否有帮助. ）
33． 在VHDL中, 定义为SIGNAL的量起到什么作用？什么时候需要定义这个量？下面的程序
ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS
SIGNAL TEM: STD_LOGIC;
BEGIN
TEM<=PIN50 AND PIN51;
PIN8 <=TEM;
END EXER2_ARCH;
和如下的程序有何区别？
ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS
BEGIN
PIN8<=PIN50 AND PIN51;
END EXER2_ARCH;
答：If PIN8 is declared in your port list, the 2 examples are identical. From a hardware design's perspective, you can think of a vhdl "signal" as an electrical signal. So basically you can declare every object as "signal". >From a simulation's perspective, there is a fundamental difference between "signal" and "variable" in vhdl. A variable is nothing more than an object that holds a value. A variable assignment occurs instantly in a vhdl simulation. Also, a variable can only exist within a process, so it cannot transfer values across processes. A signal, on the other hand, has a history of values. Whenever a signal assignment occurs, the vhdl simulator schedules an event to update the signal value after a certain period of simulation time - the signal does not get this new value instantly in the simulation time domain. Also, a signal can exists outside processes. Sounds complicated, but for most of the time you can simply use vhdl "signal" in your hardware design. （参考译文：如果在端口表中声明了PIN8, 这两个示例是一样的. 从硬件设计的角度看, 可以将vhdl "signal"视为电子信号. 因此, 基本上可以将每个对象声明为“signal”. 从仿真角度看, vhdl中的"signal" 与 "variable"是根本不同的. 变量只不过是拥有值的对象. 变量分配即时出现在vhdl仿真中. 而且, 变量只能存在于一个过程内, 因此它不能通过过程来传递值. 另一方面, 信号有多个值. 不论何时分配信号, vhdl仿真都会在某个仿真时段安排一个事件来更新信号的值. 在仿真时域里, 信号不会立即获得这个新的值. 而且信号可以存在于过程之外. 听起来好象有点复杂, 但大多数时候, 在硬件设计中可以只使用vhdl "信号". ）
答：A simple answer is to use the BUFGMUX resource in Xilinx VirtexII devices. The BUFGMUX is actually a global clock buffer in VirtexII which incoporates a smart mux to switch between 2 clock sources. More importantly, the BUFGMUX guarantees glitch-free switching between these 2 clocks, even though the select signal changes asynchronously. （参考译文：简单的方法是使用Xilinx VirtexII器件上的BUFGMUX资源. BUFGMUX实际上是VirtexII中的全局时钟缓冲, VirtexII将智能mux与2个时钟源之间的切换相结合. 更为重要的是, 即使选择信号更改不同步, BUFGMUX也能保证这两个时钟之间的无干扰切换. ）
38． I am now going to design a gray coded 16 bits counter , any efficient way to implement it in VHDL description? （要设计一个灰色编码16位的计数器, 怎么以VHDL描述来实现它？）
答：You can just use megawizard(lpm_counter) in the software to generate the counter for you, select the output language with VHDL. That should be the efficient way to implement a counter, and you don't to make additional optimize.
Because the lpm function code is the best way to fit the structure of device, which is designed by altera factory specialist who is very familiar with our device structure. （参考译文：可以使用软件里的megawizard(lpm_counter)来生成计数器, 选择带有VHDL的输出语言. 这应该是实现计数器的有效方法, 而且不用进行额外的优化.
Enhanced features available in MAX 7000E and MAX 7000S devices – Six pin- or logic-driven output enable signals
41． 在FPGA中是以何种形式实现VHDL的变量类型的？
答：There is no definite answer to this. It depends on how you write your codes. A variable in vhdl may be synthesized into a physical net, or it may not exist at all in the resulting circuit. 文：没有明确的答案. 它取决于所编写的代码. Vhdl中的变量可能同步到物理网络中, 或者根本不可能存在于结果电路中. ）
答：Most synthesizers do preserve signal names to a certain extend, usually a string is concatenated to the end of the original name. So you can still correlate the names in many cases. For those strange net names like N***, they are signals generated by the synthesizer and may not have a counterpart in the original source code. （参考译文：大多数合成器是会以某种扩展名来保存信号名称, 这些扩展名通常是连接到最初的名称末尾的字符串. 使这些名称在很多情况下仍然相关. 至于那些像N***一样奇怪的网表名称, 是由合成器生成的信号, 而且可能不会在最初的源代码中有副本. ）
答：The timing information you get from the post-layout simulation is based on worst case parameter. So you usually have better results on silicon than in simulation. For robust designs, always consider the worst case. （参考译文：从时序仿真中获得的时序信息是基于最坏情况参数的. 因此, 通常在硅片上实际操作的结果要比仿真中的好. 对于可靠的设计而言, 始终都要考虑最坏的情况. ）
44． ISE4. 2和ISE4. 1相比有何改进?
答：Here's a brief list of new features in ISE4. 2i （以下是ISE4. 2i新特性的要点）
- Device support for VirtexII Pro and CoolRunnerII （设备支持VirtexII Pro和CoolRunnerII）
- Provides 2 new source types, BMM files and ELF files, for embedded VirtexII Pro PowerPC and Microblaze processor support. BMM file is the Block RAM Memory Map file that describes the organization of Block RAM memory. ELF file is the Executable and Linkable Format file contains the executable CPU code image to be stored in Block RAM as specified in the BMM file. （提供2个新的源类型：BMM文件和ELF文件, 以支持嵌入式VirtexII Pro PowerPC和Microblaze处理器. BMM文件是“块RAM内存图”文件, 它描述了块RAM内存的结构. ELF文件是“可执行和可链接格式”文件, 它包含存储在BMM文件中指定的块RAM的可执行CPU代码图. ）
- Improved PAD file for easier to import into a spreadsheet program for viewing, sorting and printing. （改进PAD文件, 以便导入到电子表格程序中, 供查看、存储和打印）
- iMPACT now incorporates the functionality of the PROM File Formatter and Xilinx System ACE software. （iMPACT与PROM文件格式程序和Xilinx系统ACE软件的功能相结合）
- XST enhancement for better language support and preservation of internal signal names. （XST增强了语言支持, 并能保存内部信号名称. ）
For more information regarding Xilinx ISE4. 2i, please visit our website www. xilinx. com （更多有关Xilinx ISE4. 2i的信息, 请访问网站www. xilinx. com）.
45． 经常看到gate这个词. 能够具体解释一下它的含义, 例举其用法以及如何避免问题？
答：Here're a couple of examples :（举例说明）
- Never use gated clock. By gated clock we mean the clock signal comes out from combinational logic. It is well known that any signal coming out of combinational logic is prone to glitch. The result is fatal if there is a glitch on your clock signal since it will cause false triggering of FFs. A common technique to avoid gated clock is to utilize the clock enable pin on the FF. （从不使用gated clock. 这个词表示时钟信号出自组合逻辑. 众所周知, 任何出自组合逻辑的信号都容易发生故障. 由于时钟信号上的故障将导致错误触发FF, 其结果是致命的. 避免gated clock常用的技巧是利用FF上的时钟使能引脚. ）
- Never design a circuit that relies on gate delay to function. It was a common practise in the past to introduce a delay in the design by inserting a series of logic gates. This is not a recommended style in modern high speed digital design since the delay changes as new devices coming out from more advance process technologies. Also, the amount of delay changes as temperature and voltage as well. So it is not a good design practice to have circuits which relies in gate delay to function. （绝不设计依赖gate delay工作的电路. 通过插入一系列逻辑门在设计中引入延迟, 这是以前常见的作法. 而在现代高速数字设计中, 建议不要使用这种作法, 因为延迟会随采用更先进的工艺技术所制造的新器件而改变. 而且, 延迟的总量也会随温度和电压而改变. 因此依赖gate delay而工作的电路不是很好的设计. ）
答：Thank you for your input. In fact there are a number of books available in the market on Xilinx FPGA and development tools. A good example is the title "XILINX 数字系统集成技术" by Professor 朱明程, published by Southeast University Press. We will work closely with local publishers to bring out more titles on Xilinx products. （市场上还是有几本Xilinx FPGA和开发工具的书. 比较好的有朱明程教授编的《XILINX 数字系统集成技术》, 东南大学出版社出版. Xilinx公司也将会与本地出版商密切合作, 推出更多针对Xilinx产品的书籍. ）
答：After you have created the package, you need to add it to your project. In the source window, right click and select "Add source", pick the source file for your vhdl package, and then select "Vhdl package". The package will then be added to your ISE project. （参考译文：创建了这个包之后, 需要将它添加到项目中. 在源代码窗口, 右键单击并选择“Add source”, 为vhdl包选择源文件, 然后选“Vhdl package”. 这个包就添加到ISE项目中了. ）
57． 布板时, 时钟信号没有接全局时钟, 如何处理时钟使之可以更好（不需飞线）？
答：You can bring the signal back to the global clock network by inserting a BUFG. （参考译文：可以通过插入一个BUFG将一个信号返回全局时钟网络. ）
答：A possible way is to feed your 27MHz input clock to a DLL. The output of the DLL drives multiple OBUF. In this way you can create multiple copies of your input clock to drive other components on your board. You don't actually need 16 OBUFs since each OBUF can drive several loads. Note that although the DLL output can drive multiple OBUF, only the one which provides feedback to the DLL can be completely deskewed. You can also add a MAXSKEW constraint on the output net of the DLL to minimize skew among the OBUFs. This may not be a big issue since 27MHz is relatively slow. （参考译文：可能的方法是将27MHz输入时钟传递给DLL. DLL输出驱动多重OBUF. 用这种方法可以创建输入时钟的多个副本以驱动板子上的其它组件. 实际上, 不需要16个OBUF, 因为每个OBUF都可以驱动几个负载. 请注意, 虽然DLL输出能驱动多个OBUF, 但只有那个向DLL提供反馈的OBUF可以完全对称（deskewed）的. 也可以在DLL的输出量上添加MAXSKEW限制, 以最小化OBUF间的偏斜. 因为27MHz相对比较慢, 所以问题不大. ）
For more information regarding the use of DLL, please refer to the application note XAPP132 which can downloaded from the xilinx websitewww. xilinx. com（关于DLL的使用, 请参考XAPP132的应用手册. ）
59． IP CAPTION 就是核发生器, 它运行在核发生器目录下吗？
答：I think you mean "IP Capture". The IP Capture tool provides designers with an automated method to identify, capture, and document a core. The core can exist in the form of synthesizable VHDL or Verilog code, or a fixed function netlist. Once the new module has been captured, it can be installed into and distributed from a user's local copy of the Xilinx CORE Generator system. （参考译文：所指的应该是"IP Capture"吧. IP Capture工具为设计者提供了自动识别、捕获和归档核的方法. 核可以综合VHDL或Verilog码, 或固定功能连接表的形式存在. 一旦捕获了新模块, 就能够将核装入, 并从用户的本机Xilinx CORE Generator副本中分配此核. ）
Details of the IP Capture tools can be found from Xilinx website . http://www. xilinx. com/page_moved/ipcenter_e. htm?url=/ipcenter/designreuse/ipic. htm（有关IP Capture工具的详细资料, 请访问相关网站. ）
63． "Always use fully synchronous design. You never need to reply on gate delay if your design is fully synchronous. " 如果设计是完全同步的, 意思是就可以不用依靠门延时. 但在设计时, 在对和数据一同进来的控制信号进行处理后所产生的输出控制信号会滞后数据数个时钟周期, 这时就不得不对数据进行门延时, 已达到同步. 现在看来, 这是不合适的. 但是, 要用什么办法来处理这个问题而不应用门延时呢？
答：In a "fully synchronous" design, you only have 3 kinds of paths（在完全同步设计中, 只有三种途径：）
① From I/O to synchronous element. （从I/O到同步元素）
② From synchronous element to synchronous element. （从同步元素到同步元素）.
③ From synchronous element to I/O. （从同步元素到I/O）
A fully synchronous design will work as long as the delays of all these paths do not exceed the clock period. So you never need to introduce any delay. If you derive any control signal from the input signals, that control signal only goes to the 'D' or 'EN' pin of a FF, but not the 'CLK' pin. So there is no need to introduce any delay to your data. Simply speaking, you only need to design the "data" path but not the "clock" path in a fully synchrous design.
On the other hand, you can remove clock delay with the DLL in Xilinx SpartanII/Virtex devices or the DCM in VirtexII devices. （完全同步设计将工作到所有这些路径的延迟不超过时钟期间. 因此从不需要传入任何延迟. 如果从输入信号中得到任何控制信号, 则该控制信号只能传递至FF的D或EN引脚, 而不是CLK引脚. 因此, 不需要将任何延迟传入数据. 简单讲, 在完全同步设计中, 只需设计“数据”路径, 而不是“时钟”路径. ）
答：Whether you need to add external pullup resistors depends on your board design. Usually external pullup resistors are required under the following conditions（（参考译文：是否需要添加外部上拉电阻取决于电路板设计. 通常在以下条件下需要外部上拉电阻：）
- You need precise pullup values. The pullup built into the IOB is not specified to a precise resistive value since it values from batch to batch. （需要精确的上拉值. 因为it values from batch to batch, 所以然内置入IOB的上拉未指定精确电阻值. ）
- You need strong pull-up strength. The IOB pullup is relatively weak - in the order of several tens of KOhms. （需要强大的上拉动力. IOB上拉相对较弱, 只有数十千欧）
If you only want to prevent the board signal from floating, external pullup is usually not required.
You need to refer to the datasheet of the corresponding FPGA series to determine the state of the I/O during configuration. As an example, I/O pins of Virtex-E and Spartan-IIE behave as tri-state beore configuration. The HSWAP_EN pin on Xilinx Virtex-II is for enabling/disabling pullups on the user I/O pins during configuration. By default, HSWAP_EN is tied high (internal pullup resistor) which turn off pullup resistors on user I/O during configuration. （如果只想阻止板信号浮动, 通常不需要外部上拉. 需要参考相应的FPGA系列的参数表, 以确定配置过程中I/O的状态. 例如, Virtex-E和Spartan-IIE的I/O引脚在配置以前是三态的. 配置过程中, Xilinx Virtex-II 上的HSWAP_EN引脚用于启用/禁用用户I/O引脚上的上拉. 缺省情况下, HSWAP_EN系有较高内部上拉电阻, 用于在配置期间关闭用户I/O上的上拉电阻）.
答：By top down design we usually mean you partition the top level design into a number of modules first, without going into details of each of those modules. Then you start to design each module, which may involves defining more underlying submodules. The process stops when you have designed all the underlying submodules. The basic idea is to build a hierarchy which starts with less details on the top and more details as you go down the hierarchy. （参考译文：我们所谓的自顶向下设计通常是指：先将顶级设计划分为多个模块, 而不涉及这些模块的细节. 然后开始设计每个模块, 可能包括定义更多底层子模块. 当设计完成所有底层子模块后, 这个过程即完成. 基本思路是建立一个层次结构, 从顶部粗略划分开始, 越向下层越详细. ）
66． HSWAP_EN推荐接高还是低, 为什么？
答：There is no definite answer to this - it depends on whether you want the user I/Os to have pull up resistors during configurations. Therefore it is design dependent. （参考译文：没有定论. 高还是低取决于配置过程中是否要使用者I/O具有上拉电阻. 因此因设计而定. ）
答：The proper method to create and use library within ISE is （正确的方法是创建并使用ISE中的库, 过程如下：）
① Click Project->New Source and select VHDL library. （单击Project->New Source 然后选择 VHDL 库）
② Enter a name for the new library and click Next, then Finish. The new library is now visiable in the Library View tab. （为新的库输入名称, 然后单击Next-> Finish. 新的库即出现在Library View标签上. ）
③ In the library view tab, right click on the new library and then click Add Sources. （在库查看标签中, 右键单击新库, 然后单击Add Sources）
④ Choose the sources you want to add to the library. （选择要添加到库的源）
⑤ You can then use this library in your source codes. For example （然后可以在源代码中使用这个库. 例如：）
library MyLib;
use MyLib. MyPkg. all;
. . . . .
Please refer to p. 5-14 to 5-17 of the ISE User Guide which is included in the ISE Documentation CD for more details. （详情请参阅ISE文档说明光盘中的ISE User Guide 5-14至5-17）
68． 利用器件的IBIS模型能否对器件的功能进行仿真？
答：IBIS models provide information about I/O driver and receiver characteristics without disclosing proprietary knowledge of the IC design (as unencrypted SPICE models do). You need to have an IBIS simulator in order to use the IBIS model. It is not for logic simulation like vhdl or verilog models do. （参考译文：IBIS模型提供有关I/O驱动器和接收器特征的信息, 而不会透露IC设计的所有权信息, 这和未加密的SPICE模型一样. 为了使用IBIS模型, 需要有一个IBIS模拟器. 像vhdl或verilog模型一样, 它不是适用于逻辑仿真. ）
答：The tcl script is for compiling the Xilinx libraries with Modelsim. After you've compile the libraries, you need to vmap them when you simulate your design. For example, if the physical path to your compiled simprim library is d:/xilinx_sim_model/simprim, you need to map simprim to the full path by typing "vmap simprim d:/xilinx_sim_model/simprim" at the Modelsim command prompt. Then you can simulate your design by the following command "vsim -L simprim " （参考译文件：tcl脚本是为使用Modelsim编译Xilinx库的. 在编译完库之后, 仿真设计时需要vmap这些库. 例如, 如果指向已编译的simprim库的物理路径是d:/xilinx_sim_model/simprim, 则需要通过在Modelsim命令提示处输入"vmap simprim d:/xilinx_sim_model/simprim"来将simprim映射到完整路径. 然后可以使用命令"vsim -L simprim "仿真设计. ）
答：The Virtex-II HSWAP-EN pin has an internal pull-up by default to turn off the pull-up resistors at the I/O pins during configuration. You need to tie it low externally if you need to activate the pull-up at I/O pins during configuration. （参考译文：缺省情况下, Virtex-II HSWAP-EN管脚有一个内部上拉电阻, 以在配置期间关闭I/O管脚上的上拉电阻. 如果在配置过程中需要激活I/O管脚的上拉电阻, 需要将这个上拉电阻在表面上约束到较低. ）
71． PWRDWN＿B是power down pin, 可不可以不连接或上拉？
答：The PWRDWN_B pin was provided to set a Virtex-II device into a power-down mode: a low-power, inactive state. However, this feature is no longer supported in Virtex-II. To set it as inactive, the PWRDWN_B should be left at its default value, which is pulled up. (The PWRDWN_B does not require an external pull-up or pull-down. ). Please refer to Xilinx website for more details. （参考译文：PWRDWN_B管脚用于将Virtex-II器件设定为功率下降模式：低功率和不活动状态. 然而Virtex-II中已不再支持这种功能. 要在非活动状态下设定它, PWRDWN_B应该保留缺省值, 即已上拉. PWRDWN_B不要求外部上拉或下拉. 详情讲参阅Xilinx网站）.
72． spartanII不能下载, 显示done不能拉高, done上上拉电阻已接, 是何原因？
答： Here are my suggestions（有几点建议：）
-Check if the mode pin is selected correctly. （检查是否正确选择了方式管脚）.
- Check if you have selected the correct startup clock. If you are using serial mode, you need to use Cclk. If you are using jtag, you