2. Internal PCI clamp diode, combined with external series resistor to limit clamp current.
Internal PCI clamp diode is not enabled until after FPGA is configured (for hot-swap capability),
so 5V drive before configuration is complete will possibly (likely!) result in frying the FPGA input buffer.
3. Extenal voltage divider.
4. External voltage swing limiter. Example: 5V I2C signal lines limited to 2.5V with FETs on SP605 board (see page 15 of SP605 schematics). 作者: shangdawei 时间: 2014-11-22 09:21 本帖最后由 shangdawei 于 2014-11-22 09:34 编辑
The Spartan-6 data sheet is clear that the maximum input voltage (Vin) is 4.0V, so the I/Os that you have connected to 5V are degrading and will eventually fail.
Connecting a Spartan-6 output buffer to the another devices input that is expecting 5V
will not cause 5V to applied to the Spartan-6 device and will not cause degradation.
You will need to check the other device's data sheet to determine if the 3.3V level will be recognized as a logic 1 state.
74ASxx as well as other bipolar logic families like 74xx, 74ALSxx and 74Fxx all have very weak high drive once the output voltage is above about 3.5V.
This probably explains why you haven't already damaged the S6.
On the other hand 5V CMOS logic generally has significant drive at or above 4V and will damage the S6 - even with a series resistor.
Note
that S6 does not have clamp diodes to Vcco like some other families and therefore your resistor will not prevent the possibility of avalanche breakdown on the S6 inputs.
When specifying a PCI IOSTANDARD, the clamp diodes to VCCO are enabled in Spartan 3a devices.
These clamp diodes are a requirement for PCI compliance. See UG331 (v1.7) section titled Clamp Diodes beginning on page 336.
You are correct that the IO clamp diodes are always enabled in Spartan 3/3e family devices, and the diodes are NOT always enabled in Spartan 3a family devices.
The ability to disable the clamp diodes in the S3a devices is what makes the S3a family devices hot-swap compliant (connected IO pins aren't shorted when the device is unpowered).
The Fairchild Switch FSTD16211 provides 24-bits of highspeed CMOS TTL-compatible bus switching.
The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.
A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs.
The device is organized as a 12-bit or 24-bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, Port 2A is connected to Port 2B.
When OE1/2 is HIGH, a high impedance state exists between the A and B Ports.
