module pwm(clock,pwm_out,pwm_out1);
input clock;
output pwm_out;
output pwm_out1;
reg [20:0] count;
reg pwm_reg;
reg pwm_reg1;
always @ (posedge clock)
begin
count=count+1;
if (count<4) //330ns脉宽
begin
pwm_reg=1;
pwm_reg1=1;
end
else if (count<12)//660ns死区时间
begin
pwm_reg=0;
pwm_reg1=1;
end
else if(count<21'd16) //330ns负脉冲
begin
pwm_reg=0;
pwm_reg1=0;
end
else if(count==21'd240000)//12M晶振,12000000/240000=50Hz,即20毫秒
begin
unt=21'd000000;
pwm_reg=1;
pwm_reg1=1;
end
else
begin
pwm_reg=0;
pwm_reg1=1;
end
end
assign pwm_out=pwm_reg;
assign pwm_out1=pwm_reg1;
endmodule