The Spartan?-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO? technology, poweroptimized high-speed serial transceiver blocks, PCI Express? compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for
high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.
Spartan-6 FPGA主要特性:
? Spartan-6 Family:
? Spartan-6 LX FPGA: Logic optimized
? Spartan-6 LXT FPGA: High-speed serial connectivity
? Designed for low cost
? Multiple efficient integrated blocks
? Optimized selection of I/O standards
? Staggered pads
? High-volume plastic wire-bonded packages
? Low static and dynamic power
? 45 nm process optimized for cost and low power
? Hibernate power-down mode for zero power
? Suspend mode maintains state and configuration with multi-pin wake-up, control enhancement
? Lower-power 1.0V core voltage (LX FPGAs, -1L only)
? High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -4 speed grades)
Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits is between 2.6 Mb and 33 Mb depending on device size but independent of the specific user-design implementation, unless compression mode is used. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up.
This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available.
Bit-serial configurations can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal, or slave serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurations, master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal for the 8- and 16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an external clock, which can be faster or more precise than the internal clock. The available JTAG pins use boundary-scan protocols to load bit-serial configuration data.
图1.Spartan-6 FPGA在汽娱乐系统应用框图
Serving as a companion to the host processor, a single Spartan-6 LX45T FPGA supports audio/video acceleration, graphics subsystem, and vehicle networking functions.
图2.Spartan-6 FPGA在平板显示器应用框图
High-Resolution Video Flat-Panel Display with Dynamic Backlight Control
Achieve higher image quality while reducing power and cost using Spartan-6 FPGAs withintegrated serial I/O capabilities.
图3.Spartan-6 FPGA在视频监视系统应用框图
Surveillance Image Capture and Analytics Engine
Integrate sensor interfacing, video analytics, image enhancement and network interfacing in a single Spartan-6 LX150T FPGA.
The Spartan?-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,400 to 148,000 logic cells, with half the power consumption of previous Spartan families and faster, more comprehensive connectivity.
Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan?-6 family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks,SelectIO? technology, power-optimized high-speed serial transceiver blocks, PCI Express? compatible Endpoint blocks, advanced system-level power management modes, autodetect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease-of-use. Spartan?-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins.
SP601评估套件
The SP601 Evaluation Kit is based on the XC6SLX16-2CSG324 Spartan-6 FPGA. This FPGA contains 14,579 logic cells, a rating that reflects the increased logic capacity offered by the new six-input LUT architecture.
SP601评估套件主要特性:
The SP601 designs demonstrate Spartan-6 FPGA features using the SP601 evaluation
board. These features include:
