Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity atel2_bin is
port( txclk: in std_logic;????????????????????? --2400Hz的波特率时钟
????? reset: in std_logic;????????????????????? --复位信号
??????? din: in std_logic_vector(15 downto 0);? --发送的数据
????? start: in std_logic;????????????????????? --允许传输信号
?????? sout: out std_logic????????????????????? --串行输出端口
????????? );
end atel2_bin;
architecture behav of atel2_bin is
signal thr,len: std_logic_vector(15 downto 0);
signal txcnt_r: std_logic_vector(2 downto 0);
signal sout1: std_logic;
signal cou: integer:=0;
signal oddb:std_logic;
type s is(start1,start2,shift1,shift2,odd1,odd2,stop1,stop2);
signal state:s:=start1;??
begin
? process(txclk)?????
??? begin
????? if rising_edge(txclk) then
?????????? if cou3 and state=stop2) then thr'0');
???????????????? sout1
????????????? if start='1' then????????????
???????????????? if cou=3 then
??????????????????? len'0');???
???????????????? state
????????????? oddb???????? --奇校验位
????????????? if ddb='1' then
???????????????? sout1
????????????? sout1
????????????? tsr1:=thr(15 downto 8);
???? oddb2:=thr(15 downto 8);?
????????????? sout1'0');?
????????????? state
????????????? oddb?????? --奇校验位
?if ddb='1' then
???????????????? sout1??
????????????? sout1<='1';??? --停止位????
????????????? if len="0000000000000000" then
???????????????? state<=stop2;?????????????????
????????????? else
???????????????? state<=start1;???????????????
???????????????? len<=len-1;
????????????? end if;????????????????????????
???????? end case;
???????? end if;????????????????
?? end process;?
? sout<=sout1;
end behav;
