LIbRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY parrial IS
PORT
(
STLD : IN STD_LOGIC;
CLK : IN STD_LOGIC;
Q1 : IN STD_LOGIC;
Q2 : IN STD_LOGIC;
Q3 : IN STD_LOGIC;
Q4 : IN STD_LOGIC;
Q5 : IN STD_LOGIC;
Q6 : IN STD_LOGIC;
Q7 : IN STD_LOGIC;
Q8 : IN STD_LOGIC;
shiftout : OUT STD_LOGIC
);
END parrial;
ARCHITECTURE parrial_architecture OF parrial IS
signal latch : std_logic_vector (7 downto 0) ;
begin
process (CLK,STLD,Q1 ,Q2 ,Q3,Q4 ,Q5 ,Q6 ,Q7,Q8)
begin
if (CLK’event and CLK=‘1’) then
if (STLD =‘1’) then
latch(7) <= Q8;
latch(6) <= Q7;
latch(5) <= Q6;
latch(4) <= Q5;
latch(3) <= Q4;
latch(2) <= Q3;
latch(1) <= Q2;
latch(0) <= Q1;
else
latch(0) <= latch(1) ;
latch(1) <= latch(2) ;
latch(2) <= latch(3) ;
latch(3) <= latch(4) ;
latch(4) <= latch(5) ;
latch(5) <= latch(6) ;
latch(6) <= latch(7) ;
latch(7) <= ‘1’;
end if ;
end if ;
end process;
shiftout<=latch(0);
END parrial_architecture;