MSP430F522x和MSP430F521x设计注意事项

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1.Split-Supply I/O Systems
          For split-supply I/O systems, the split supplies are connected to the VCC (DVCC and AVCC) and DVIO pins. Supply voltage at DVCC and AVCC pins (VCC) is used to provide device power, and the supply voltage at the DVIO pin (VIO) is used to supply the I/O rail of the "DVIO supplied I/O pins". The recommended VCC supply voltage ranges from 1.8 V to 3.6 V (see note A on Figure 1) and, therefore, these devices do not operate at nominal 1.8 V (that is, 1.8 V ± 10%) supply voltage level. The VIO supply voltage ranges from 1.62 V to VCC(c) and is useful in applications that interface with nominal 1.8-V I/O interface (that is, 1.8 V ± 10%).
           
          A The recommended VCC supply voltage range of 1.8 V to 3.6 V is applicable to the VCORE setting of PMMCOREVx = 0. See the device data sheet for the VCC supply voltage ranges at different VCORE settings. B It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power-up and operation. C See the F522x and F521x data sheet [1] for the VIO supply voltage range. Figure 1. Split Supply I/O Systems.
           
          2. DVIO Supplied I/Os
          A group of general-purpose I/Os reside on the DVIO supply domain and are called DVIO supplied I/Os. On the MSP430F522x devices, the following I/Os reside on the DVIO supply domain: Port1 (P1.4 to P1.7), Port2, Port3, Port4, and Port7. The remaining port I/Os reside on the DVCC supply domain.
           
          In the device data sheet, these I/O ports are highlighted in the functional block diagrams and are also pointed out in the "Terminal Functions" table for respective I/O pins. Also, the electrical characteristics of I/Os in the DVIO and the DVCC domains are specified separately in the device data sheet [1].
           
          3 Secondary Digital Functions on DVIO Supplied I/Os
          The DVIO supplied general-purpose I/Os are multiplexed with other digital functions in the device, and these digital functions’ I/O circuits are also powered from DVIO. On the F522x and F521x devices, some of the secondary digital functions that are shared with the DVIO supplied I/Os include timer capture compare functions, serial communication functions (USCI UART, SPI, or I2C), comparator output, SMCLK output, and MCLK output. See the Terminal Functions table in the device data sheet [1] for details.
           
          On the F522x and F521x devices, Port4 supports port mapping and resides on the DVIO supply domain. Any of the secondary digital functions specified in the port mapping table can be mapped to Port4, and their respective I/O circuitry is supplied by DVIO. See the port mapping table in the Peripherals section of the data sheet [1] for details.
           
          NOTE: In split supply I/O systems, if external pullup resistors are connected to any of the DVIO supplied pins (for example, the USCI I2C pins – SDA and SCL), tie the external pullups to the DVIO supply and not to DVCC.
           
          Other DVIO supplied digital pins on the F522x and F521x devices include: • BSLEN – BSL enable pin used by the DVIO supplied BSL interface (see Section 7). By default, this pin has a nonconfigurable internal pulldown resistor enabled. • RST/NMI – DVIO supplied reset pin multiplexed with NMI functionality. See Section 5 for details of the reset functionality.
           
          4 Split-Supply Power-Up or Power-Down Sequence
          For split-supply I/O systems, it is required that the VIO ≥ VCC during the ramp up phase of VIO and VCC. During VCC and VIO power down, it is required that VIO ≥ VCC during the ramp down phase of VIO and VCC. Figure 2 is an excerpt from the data sheet.
           
          NOTE: The device supports continuous operation with VCC = VSS while VIO is fully within its specification. During this time, the general-purpose I/Os that reside on the VIO supply domain are configured as inputs and pulled down to VSS through their internal pulldown resistors. RST/NMI is high impedance. BSLEN is configured as an input and is pulled down to VSS through its internal pulldown resistor. When VCC reaches above the BOR threshold, the general-purpose I/Os become high-impedance inputs (no pullup or pulldown enabled), RST/NMI becomes an input pulled up to VIO through its internal pullup resistor, and BSLEN remains pulled down to VSS through its internal pulldown resistor. Figure 2. VCC and VIO Power Sequencing
           
          5 Reset and NMI Pin Functionality
          On the F522x and F521x devices, there are two reset pins: • RSTDVCC/SBWTDIO: resides on the DVCC supply domain • RST/NMI: resides on the DVIO supply domain The device can be held in reset by asserting a low on either of the two reset pins. However, the NMI pin functionality is available only on the RST/NMI pin and is not multiplexed with the RSTDVCC pin.
           
          The RSTDVCC pin has an internal pullup that is always enabled and is not configurable. The RST/NMI pin has configurable internal pullup and pulldown resistors available. By default, the internal pullup resistor on the RST/NMI pin is enabled. The SYSRSTUP and SYSRSTRE bits in the reset pin control register (SFRRPCR) are used to select either the internal pullup or pulldown and to enable them, respectively.
           
          If the RST/NMI pin is unused, select and enable the internal pullup resistor, or connect an external pullup resistor (47 kΩ recommended) to the pin.
           
          NOTE: Because all of the 4-wire JTAG pins (on Port J) reside on the DVCC supply domain, use the RSTDVCC pin which also resides on the DVCC supply domain for the JTAG interface and not the DVIO supplied RST/NMI pin. For more details, see the "JTAG Pin Requirements and Functions" table in the device data sheet [1].
           
          3SLAA558–November 2012 Designing With MSP430F522x and MSP430F521x Devices Submit Documentation Feedback Copyright ? 2012, Texas Instruments Incorporated
          XT1 and XT2 Oscillators in Bypass Mode www.ti.com.
           
          6 XT1 and XT2 Oscillators in Bypass Mode
          The F522x and F521x devices have two on-chip crystal oscillators: • XT1: low-frequency crystal oscillator  XT2: high-frequency crystal oscillator Both XT1 and XT2 oscillators can be operated in crystal bypass mode, in which external clock signals are input to the XIN and XT2IN pins, respectively, and the oscillators associated with XT1 and XT2, respectively, are powered down. By default, the XIN and XT2IN pins reside on the DVCC supply domain and require the external clock signal to meet the data sheet specified input specifications for I/Os in DVCC domain.
           
          Additionally, the F522x and F521x devices support XT1 and XT2 bypass operation with external clock inputs that reside on the DVIO supply domain. Setting the XT1BYPASSLV and XT2BYPASSLV bits in the UCSCTL9 register enables the XT1 and XT2 bypass operations, respectively, with external clock signals that swing from 0 V to DVIO.
           
          In both the cases, the external clock input frequency must meet the data sheet parameters for the chosen mode.
           
          On the F522x and F521x devices, the XIN and XOUT (XT1) and XT2IN and XT2OUT (XT2) pins are multiplexed with the general-purpose I/O pins that reside on the DVCC supply domain. When the XT1 and XT2 oscillators are configured in crystal bypass mode, the XIN and XT2IN pins, respectively, can accept external clock input signals, and the XOUT and XT2OUT pins, respectively, can be configured as general- purpose I/O pins that are supplied by DVCC.
           
          7 Bootstrap Loader (BSL)
          The BSL enables users to program the flash memory or RAM using a serial interface. The F522x and F521x devices come with UART as the default BSL serial interface. Access to the device memory via the BSL is protected by a user-defined password. Because the F522x and F521x devices have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO supply domains.
           
          Table 1 shows the various device pins used for DVCC and DVIO supplied BSL interfaces. For more details, see the BSL description in F522x and F521x data sheet [1].
           
          Table 1. DVCC and DVIO Supplied BSL Interfaces
          BSL Function DVCC Supplied BSL Interface DVIO Supplied BSL Interface
          External Reset RSTDVCC/SBWTDIO RST/NMI
          Enable BSL TEST/SBWTCK BSLEN
          Data Transmit P1.1 (Timer_A UART) P3.3/UCA0TXD (USCI_A0 UART)
          Data Receive P1.2 (Timer_A UART) P3.4/UCA0RXD (USCI_A0 UART)
          Device Power Supply DVCC, AVCC DVCC, AVCC
          I/O Power Supply DVIO DVIO
          Ground Supply DVSS DVSS
          For single-supply systems (DVIO connected to DVCC) in which the DVCC supplied BSL interface is used, specific BSL entry and exit sequences are generated using the RSTDVCC/SBWTDIO and TEST/SBWTCK pins. These are the standard RESET and TEST based BSL entry and exit sequences that apply to all non- USB F5xx and F6xx devices, and the standard TI supplied BSL tools can be used to access the device.
           
          For split-supply I/O systems in which the DVIO supplied BSL interface is used, specific BSL entry and exit sequences should be generated using the RST/NMI and BSLEN pins, and these sequences apply only to the DVIO supplied BSL interface.
           
          4 Designing With MSP430F522x and MSP430F521x Devices SLAA558–November 2012 Submit Documentation Feedback Copyright ? 2012, Texas Instruments Incorporated
          BSLEN
          RST
          BSLEN
          RST
          www.ti.com Bootstrap Loader (BSL)
           
          7.1 BSL Entry Sequence for DVIO Supplied BSL Interface
          BSLEN is the BSL enable pin with internal pull down resistor enabled and the BSL entry sequence involves toggling the RST/NMI pin (high-low-high transition) with the BSLEN pin pulled high (see Figure 3).
           
          A The minimum timing for this sequence must be within the limits specified for the corresponding pins in the data sheet.
           
          Figure 3. BSL Entry Sequence for DVIO Supplied BSL Interface
          Note 2:The BSLEN pin need not be pulled high during the entire period when the device is in BSL mode. However, the BSLEN pin is required to be pulled high for a minimum period of time after the RST/NMI pin goes low-high for proper BSL invoke. See the F522x and F521x data sheet [1] for the timing specifications.
           
          7.2 BSL Exit Sequence for DVIO Supplied BSL Interface
          The BSL exit sequence of the DVIO supplied BSL interface involves toggling the RST/NMI pin (high-low- high transition) with the BSLEN pin pulled low (see Figure 4).
           
          A The minimum timing for this sequence must be within the limits specified for the corresponding pins in the data sheet.
           
          Figure 4. BSL Exit Sequence for DVIO Supplied BSL Interface
          For complete description of the BSL entry and exit sequences (for both DVCC and DVIO supplied BSL interfaces), features and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).
           
          5SLAA558–November 2012 Designing With MSP430F522x and MSP430F521x Devices Submit Documentation Feedback Copyright ? 2012, Texas Instruments Incorporated
          Debugger Connections www.ti.com
           
          8 Debugger Connections
          The F522x and F521x devices support both the standard four-wire JTAG interface and the two-wire Spy- Bi-Wire interface.
           
          8.1 JTAG Standard Interface
          The F522x and F521x support the standard JTAG interface. The four signals for receiving and sending JTAG signals are shared with Port J general-purpose I/Os and are powered by the DVCC supply domain. The JTAG pin requirements are shown in Table 2. With the connections below, the JTAG can be used to interface with the MSP430 development tools and device programmers.
           
          Table 2. Standard JTAG Interface Pins
          DEVICE SIGNAL DIRECTION FUNCTION
          PJ.3/TCK IN JTAG clock input
          PJ.2/TMS IN JTAG state control
          PJ.1/TDI/TCLK IN JTAG data input, TCLK input
          PJ.0/TDO OUT JTAG data output
          TEST/SBWTCK IN Enable JTAG pins
          RSTDVCC/SBWTDIO IN External reset
          DVCC, AVCC Device power supply
          DVIO I/O power supply
          DVSS Ground supply
           
          For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tool User’s Guide (SLAU278) [4].
           
          8.2 Spy-Bi-Wire Interface
          In addition to the standard JTAG interface, the F522x and F521x support the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with the MSP430 development tools and device programmers. The Spy-Bi-Wire signals are powered by the DVCC supply domain and the interface pin requirements are as shown in Table 3.
           
          Table 3. Spy-Bi-Wire Interface Pins
          DEVICE SIGNAL DIRECTION FUNCTION
          TEST/SBWTCK IN Spy-Bi-Wire clock input
          RSTDVCC/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
          DVCC, AVCC Device power supply
          DVIO I/O power supply
          DVSS Ground supply
          For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tool User’s Guide (SLAU278) [4].
           
          8.3 Debugging Without DVIO
          It is safe and possible to have only DVCC and not DVIO connected to the device for the purpose of simple device debugging. However, DVIO pins and their related functions are not available in this mode. Additional effects includes higher leakage current during debug; therefore, this option is suitable only for preliminary debugging of the device.
           
          6 Designing With MSP430F522x and MSP430F521x Devices SLAA558–November 2012 Submit Documentation Feedback Copyright ? 2012, Texas Instruments Incorporated www.ti.com References.
           
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