Bus Blaster v2

liyf

说实在的，这个也是不错的方案，可以参考下，原文：
Bus Blaster v2 design overview                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             

Bus Blaster v2 is an experimental, high-speed JTAG debugger for ARM processors, FPGAs, CPLDs, flash, and more. Thanks to a reprogrammable buffer, a simple USB update makes Bus Blaster v2 compatible with many different  JTAG debugger types in the most popular open source software.

• Based on FT2232H with high-speed USB 2.0
• Buffered interface works with 3.3volt to 1.5volt targets
• Reprogrammable buffer is compatible with multiple debugger types
• Compatible with 'jtagkey', 'KT-link' programmer settings in OpenOCD, urJTAG, and more
• Should support Serial Wire Debug when available
• Mini-CPLD development board: self programmable, extra CPLD pins to header
• Open source (CC-BY-SA)
  

Bus Blaster v3 is now available for $34.95. Bus Blaster v2 is available now for $34.95. Each unit is tested with a real JTAG target before it ships.
Read about the design below.
Overview

The Bus Blaster is used to program and debug devices with a JTAG interface like ARM processors, CPLDs, flash memory, and more.A FT2232H USB chip gives us two high-speed JTAG interfaces. The 16 pins of the primary interface are connected to a CoolRunner-II CPLD. The CPLD is a programmable buffer that translates between the FT2232H at 3.3volts, and a 1.5volt to 3.3volt target.
Many JTAG debuggers use the FT2232 chips, but they have slightly different buffers. The CPLD can be programmed to imitate many of them, so it works out of the box with our favorite open source debugging apps. Updates are done over USB using the second JTAG interface on the FT2232H.
This project was inspired by a forum post that linked to a Texas Instruments' XDS100 programmer. TI's design is essentially the same, but we moved the CPLD JTAG connection to the second JTAG interface for easier reprogramming. Bus Blaster v2 was developed in a public forum, and progress was documented on a wiki.

Hardware

Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.
FT2232H

The FT2232H is a powerful USB to serial communication chip. It has an MPSSE feature that provides a simple USB to JTAG converter (and UART, I2C, or SPI). Most DIY JTAG debuggers use this chip, as do many commercial models.
Bus Blaster v2 uses the 'H' version of the chip, the latest 3.3volt revision that supports JTAG adaptive clocking. The circuit is based on a reference design from the FT2232H datasheet.

• See the FT2232H breakout board documentation for a complete explanation of the FT2232H reference circuit
  

Buffered interface


The buffer translates voltage levels between the FT2232H (3.3volts) and a JTAG device (1.5volts-3.3volts). The four main JTAG IO pins (TDI, TDO, TCK, TMS) are fixed on the FT2232, but the other reset and control pins vary among programmers.
Bus Blaster v2 is buffered by a programmable logic chip (CPLD) that can be updated to imitate many common buffer types. The CPLD is connected to the secondary JTAG interface on the FT2232, so uploading a new buffer type is done entirely from software over USB.
CPLD

An XC2C32A CoolRunner-II CPLD (IC9) is used for the buffer. These are the smallest available CPLDs from Xilinx, and they only cost around $1 in onesies.
The CPLD core requires a 1.8volt supply, which is conveniently available from the FT2232. The JTAG and IO pins are powered by a separate supply between 1.5 and 3.3volts. Each supply pin gets a 0.1uF capacitor.
This chip is perfect for voltage translation because the IO pins are divided into two groups that can operate from different power supplies. We connected one group to the FT2232 and the 3.3volt FT2232 power supply. The other group connects to the JTAG target, and operate from a 1.5volt to 3.3volt target supply.
You must connect the target power supply to the bufferThe buffer is powered by the target, 1.5volts to 3.3volts onlyPut a header on JP4 to power the target from the programmer. 3.3volts max 200mAThe buffer is NOT 5volt compatible.
We brought the extra CPLD pins to a header. The Bus Blaster v2 can also be used as a simple CoolRunner-II CPLD development board.

• See Xilinx CoolRunner-II CPLD quick start guide for more
  

Buffer logic
New buffer logic is designed using simple schematic entry, Verilog, or VHDL, and the free ISE Webpack software from Xilinx.

• See CPLD development tutorials
  

Here are two examples of buffer logic to give you an idea how flexible the design can be.

• See Bus Blaster v2 & v3 buffer logic for the latest buffers and programming instructions
  

JTAGkey compatible

The JTAGkey is probably the most commonly used buffer configuration among DIY FT2232-based JTAG programmers. It is compatible with OpenOCD, urJTAG, and more.
Program the Bus Blaster 2 with this buffer and it will work with most applications that support JTAGkey type debuggers.

• JTAGkey buffer overview
  

KT-link compatible

OpenOCD and urJTAG will soon support new Serial Wire Debug and Serial Wire Viewer JTAG protocols via a KT-link type buffer.
Program the Bus Blaster 2 with this buffer and it can support SWD in OpenOCD and urJTAG. Special thanks to the developers of libswd for help implementing this buffer on the Bus Blaster.
Pinout

JTAG header pinout

pin	Fixed FT2232 pin	description	direction
VTG		Voltage target	input
TRST		Reset output	output
TDI	ADBUS1	JTAG data in to target	output
TMS	ADBUS3	JTAG state machine update	output
TCK	ADBUS0	JTAG clock in to target	output
RTCK	ADBUS7	System return clock	input
TDO	ADBUS2	JTAG data out from target	input
TSRST		Bi-directional reset pin	inout
DBGRQ		Debug request	output
DBGACK		Debug acknowledge	input

9 CPLD pins are brought to the 20pin JTAG header. The pins are labeled, but the CPLD buffer makes placement totally arbitrary.
Not all pins are supported by all buffers and/or applications
The VTG pin should be connected to the power supply of the device under test. The JTAG pin outputs will then work at the same voltage.
The target must generally supply power to the VTG pin!
The JTAG pins can also operate from the 3.3volt on-board power supply by placing a jumper on header JP4. In this configuration the VTG pin can supply up to 100mA @ 3.3volts to the test device.
PCB

We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.
Partslist
Click for a full size placement image.
partslist

Part	Quantity	Value	Package
C1-C7,C13-C21	16	100nF	C805
C8	1	3.3uF	SMC_A
C9,C10	2	27pF	C805
C11,C12,C22	3	4.7uF	SMC_A
IC1	1	FT2232H	LQFP64
IC2	1	93LC46B	SOIC8
IC3	1	LD1117-3.3	SOT223
IC9	1	XC2C32A_VQ44_2	VQ44
JP1-4	1	0.1" pin header	1X0X
JTAG	1	2x10 shrouded header (0.1”)	PINHEAD_-_COPY_PINSHRD_PTH_2X10
L1,L2	2	ferrite bead (800mA+)	FB805
PWR	1	LED	CHIPLED_0805
R1	1	12K 1%	R805
R2	1	1K	R805
R3,R4,R5	3	10K	R805
R6	1	2.2K	R805
R10	1	1K	R805
USB	1	USB mini-B connector	CONN_USB_MINI-B
X1	1	12MHz crystal	4X6

• Shopping cart at Mouser
  

The latest sources and distributors are in the master partlist. See something missing? Please let us know.
Taking it further
The reprogrammable buffer logic should future proof Bus Blaster v2. Already we were able to add Serial Wire Debug support by creating a new buffer implementation.
A minor revision in the next batch has a few minor changes:

• Jumper JP4 moved to edge of PCB
• LED and button connected to CPLD for demos
  

An eventual point revision is planned with:

• 3.3volt over voltage protection for the CPLD
• Serial resistors on the JTAG pins
  

v3 may use a 100pin CPLD to include support for SWV, another reduced pin-count JTAG protocol.

radiotube

沙花，谢谢楼主分享。。