3.3V-5V电平双向转换电路收集

shangdawei · 发表于 2014-11-27 11:21:39

AN97055.pdf (75.3 KB, 下载次数: 4)

Bi-Directional MOSFET Voltage Level Converter 3.3V to 5V

When connecting 3.3V devices and 5V devices voltage level conversion is required. The following circuit will allow this to be done bi-directionally

Low Side Control

When the low side (3.3V) device transmits a '1' (3.3V), the MOSFET is tied high (off), and the high side sees 5V through the R2 pull-up resistor. When the low side transmits a '0' (0V), the MOSFET source pin is grounded and the MOSFET is switched on and the high side is pulled down to 0V.

High Side Control

When the high side transmits a '0' (0V) the MOSFET substrate diode conducts pulling the lowside down to approx 0.7V,
this is also low enough to turn the MOSFET on, further pulling the low side down.
When the high side transmits a '1' (5V) the MOSFET source pin is pulled up to 3.3V and the MOSFET is OFF.

Note This works with I2C and other open collector type gates

No 3.3V Supply?

If you dont have access to the 3.3V supply (maybe the 3.3V voltage regulator is on a breakout board)
you can simply tie the gate to 3.3V via a simple voltage divider

在电平转换器的操作中要考虑下面的三种状态：

1 没有器件下拉总线线路。

“低电压”部分的总线线路通过上拉电阻Rp 上拉至3.3V。
MOS-FET 管的门极和源极都是3.3V，所以它的VGS 低于阀值电压，MOS-FET 管不导通。
这就允许“高电压”部分的总线线路通过它的上拉电阻Rp 拉到5V。
此时两部分的总线线路都是高电平，只是电压电平不同。

2 一个3.3V 器件下拉总线线路到低电平。

MOS-FET 管的源极也变成低电平，而门极是3.3V。
VGS上升高于阀值，MOS-FET 管开始导通。
然后“高电压”部分的总线线路通过导通的MOS-FET管被3.3V 器件下拉到低电平。
此时，两部分的总线线路都是低电平，而且电压电平相同。

3 一个5V 的器件下拉总线线路到低电平。

MOS-FET 管的漏极基底二极管“低电压”部分被下拉直到VGS 超过阀值，MOS-FET 管开始导通。
“低电压”部分的总线线路通过导通的MOS-FET 管被5V 的器件进一步下拉到低电平。
此时，两部分的总线线路都是低电平，而且电压电平相同。

这三种状态显示了逻辑电平在总线系统的两个方向上传输，与驱动的部分无关。

状态1 执行了电平转换功能。状态2 和3 按照I2C 总线规范的要求在两部分的总线线路之间实现“线与”的功能。

除了3.3V VDD1 和5V VDD2 的电源电压外，还可以是例如：2.5V VDD1 和12V VDD2。

在正常操作中，VDD2必须等于或高于VDD1（在开关电源时允许VDD2 低于VDD1）。

2.5V 也可以和5V双向转换

Since the outer resistors and the drawing are bus resistors which hold the bus level at HIGH level when no device is pulling it done to LOW, this is state one.

So if both lines, left and right are not low, no current is allowed to flow from both transistor bases.
So no amplified current is flowing.

This is state 1.

At state 2 the left 3.3V-side is pulled to LOW.
Following this the lower transistor will have a current flowing from base to emitter.
According to the basics of the transistor there is current allowed to flow between collector and emitter and the right side receives a LOW as well.

State 3 is described by polling LOW on the right side. T
his happens like state 2 but instead the upper transistor is made conductive.

Two transistor circuit replaces IC

iic.pdf (177.3 KB, 下载次数: 0)

The outer most resistors are pull-up resistors for the I2C bus.

A device that pulls a line down, has to pull down the current through both resistors (on the 3.3V side, and on the 5V side)
and also the current through the base of the transistor.

Typical values for the resistors 10k for all of them.

Warning:

There are some disadvantages with these 4 transistors.

If a line is pulled low, a current from the base to the emittor will turn that transistor on.

But the other transistor will leak current from the base to the collector.

That current will reduce the current in the first transistor.

I have build this circuit and it is doing well, but it doesn't meet the full I2C specifications

when the pull-up resistors are less then 4k7.